IEEE CEDA
SWEAT 2026

Girishankar G is Deputy Director of the Compute and Artificial Intelligence group at MediaTek Bangalore, where he is responsible for high-speed, low-power CPU and GPU processors, along with custom circuit SRAM design and methodologies.

He co-founded Immensa Semiconductors, a foundation-IP company that was later acquired by MediaTek. Earlier in his career, he served as a Senior Technologist responsible for Texas Instruments’ standard-cell libraries.

Girishankar holds 14 US patents and has authored 5 IEEE publications.

Vasudevan Perincheeri is Co-Founder and Executive Director at Sophrosyne Semiconductor, where he has built a semiconductor design-services organization from the ground up — scaling a team of around 90 engineers across analog layout, standard-cell layout, circuit design, library characterization, and EDA automation, while setting up the company’s core operating, hiring, and training processes from scratch.

With over two decades in the semiconductor industry, Vasudevan has held senior program-management and delivery leadership roles across the ecosystem. At Karmic Design, he progressed from Senior Engineer to Technical Lead and Project Manager, leading teams of 12–15 engineers for Texas Instruments and supporting 50+ standard-cell libraries across 18 foundry processes including TSMC, UMC, and GlobalFoundries.

He went on to lead Mirafra Technologies’ Design Excellence Center at Manipal as Business Manager & Site Director, scaling engineering teams for customers including Qualcomm, and later served as Account Director at UST Global, managing key VLSI and Embedded semiconductor accounts across India and APAC.

Most recently, as Program Director at Tech Mahindra Cerium, he led the integration of Cerium into Tech Mahindra, coordinating customer contracts, delivery operations, and change management through the transition.

Across his career, Vasudevan has built scalable training and mentoring models that convert junior engineers into deployment-ready semiconductor talent — a focus that continues to shape his work at Sophrosyne Semiconductor today.

Sri Harsha Reddy Kaliki is a seasoned engineering professional with 14 years of experience in flow methodology development across Analog, Digital, and Mixed-Signal domains. With deep expertise in building and optimizing design and verification flows, he has consistently driven efficiency, quality, and innovation in semiconductor development processes.

He currently leads the Methodology team at SSIR, where he is responsible for defining and advancing flow strategies that enable cutting-edge chip design. In addition to his core methodology leadership, he is actively driving AI enablement initiatives, exploring how artificial intelligence can transform traditional design flows and accelerate time-to-market.

Abhilash Karthik is a Director at Samsung Semiconductor.

Zameer Iqbal is a PDK Lead at Samsung R&D.

Gururaj Bankapur is Director and Member Technical Staff at Karmic Design Pvt Ltd.

Nikhil Singla is a Silicon Engineer at Google.

John JM Tan is Assistant Vice President at Tata Electronics Private Ltd.

Rajeela Deshpande serves as Sponsorship Chair for IEEE CEDA SWEAT 2026 and moderates the Guidance Panel.

Sundar has been at Cadence for 15+ years, with an overall experience of 25+ years in the field of SoC & IP Verification.

Sundar leads the Cadence Advanced Verification Solutions field team for the India region and drives the Advanced AI-ML Verification Solutions in the region.

Praveen Kumar is an Application Engineering Director at Cadence Design Systems with over 21 years of experience in semiconductor design verification, functional safety, and advanced verification methodologies.

He works closely with leading semiconductor companies to deploy innovative verification solutions spanning simulation, formal verification, coverage closure, debug, and AI-driven verification flows.

Prior to Cadence, he held senior technical leadership positions at STMicroelectronics, Infineon Technologies, and Freescale Semiconductor, leading IP, subsystem, and SoC verification programs across automotive, networking, and communication domains.

His expertise includes deployment of advanced verification methodologies for complex SoC and automotive designs, including ISO 26262 and ASIL-compliant verification flows.

He is actively involved in advancing the adoption of AI-powered verification technologies, including Cadence Verisium solutions, to improve verification productivity and quality.

Ketki Gosavi is a Sr Principal Application Engineer at Cadence.

Gnaneshwara Tatuskar is an Architect AE at Cadence Design Systems.

Goutham S is with Cadence.

Saurav Choudhary is a Lead Application Engineer at Real Intent Inc., specializing in static verification and signoff for high-performance CPU, GPU, and NoC designs. His expertise spans Lint, CDC, RDC, connectivity, security, and power verification, with a focus on addressing complex design challenges in collaboration with cross-functional teams.

Prior to joining Real Intent, he was a Digital Design Engineer at NXP Semiconductors, where he worked on RTL and microarchitecture for hardware accelerator IPs. He has co-authored technical papers presented at DAC 2024 and DAC 2025 on advanced static verification methodologies.

Sanathraj Narayan brings over a decade of experience in AI/ML, data science, and analytics, with a strong track record of building and deploying machine learning solutions at scale.

In the past, he was at Ericsson, where he led model development and implementation for network rollout and forecasting use cases. He has also worked at Mindtree and KPMG, focusing on predictive analytics, scalable ML models, and enterprise AI solutions.

Sanath is passionate about industrializing AI/ML models and driving real-world impact. He has been an active speaker at AI/ML conferences like Cypher and DataHack Summit, sharing insights on LangChain and LLM-based applications.

Sriram Muthukumar is an ASIC Design Engineering Manager at Meta.

Anil Dalwani is Senior Director of Engineering at Analog Devices.

Joy Thomas is Deputy Director & Global Segment Manager for Factory Automation Solutions (Electronics) at Applied Materials.

Utkarsh Garg is a Senior Staff Engineer at Samsung Semiconductor India R&D.

Palash Khandale is a Staff Engineer at Arm.