IEEE CEDA
SWEAT 2026

Rajesh oversees Samsung Semiconductor India’s operations across the Memory, System LSI, and Foundry businesses, while spearheading global business strategy, technology innovation, and organizational growth. With more than three decades of industry experience, he has been instrumental in driving excellence in product development, fostering innovation, and building high-performing engineering teams. Under his leadership, the Bengaluru centre has evolved into a strategic hub for cutting-edge semiconductor research, development, and global innovation.

His diverse career spans Computer Architecture, Compiler Design, Satellite Communication Systems, Telecom Infrastructure, Mobile Devices, and Semiconductors. Prior to joining Samsung, he served as a Satellite Systems Engineer at Hughes Network Systems, USA, and was associated with Motorola India, where he contributed to the development of compilers for microcontroller technologies.

An accomplished innovator with multiple global patents to his credit, Rajesh also served on the Executive Council and Board of Directors of the India Electronics and Semiconductor Association (IESA) from 2016 to 2018, contributing to the advancement of India’s electronics and semiconductor ecosystem.

Rajesh holds an MBA from the University of Maryland and a Master’s degree in Computer Engineering from Indian Institute of Technology Kharagpur.

A strong advocate of holistic well-being, he believes that mental and physical wellbeing are powerful complements to a successful corporate career. Outside of work, he actively pursues yoga, participates in triathlons, and nurtures his passion for music.

Girishankar G is Deputy Director of the Compute and Artificial Intelligence group at MediaTek Bangalore, where he is responsible for high-speed, low-power CPU and GPU processors, along with custom circuit SRAM design and methodologies.

He co-founded Immensa Semiconductors, a foundation-IP company that was later acquired by MediaTek. Earlier in his career, he served as a Senior Technologist responsible for Texas Instruments’ standard-cell libraries.

Girishankar holds 14 US patents and has authored 5 IEEE publications.

Vasudevan Perincheeri is Co-Founder and Executive Director at Sophrosyne Semiconductor, where he has built a semiconductor design-services organization from the ground up — scaling a team of around 90 engineers across analog layout, standard-cell layout, circuit design, library characterization, and EDA automation, while setting up the company’s core operating, hiring, and training processes from scratch.

With over two decades in the semiconductor industry, Vasudevan has held senior program-management and delivery leadership roles across the ecosystem. At Karmic Design, he progressed from Senior Engineer to Technical Lead and Project Manager, leading teams of 12–15 engineers for Texas Instruments and supporting 50+ standard-cell libraries across 18 foundry processes including TSMC, UMC, and GlobalFoundries.

He went on to lead Mirafra Technologies’ Design Excellence Center at Manipal as Business Manager & Site Director, scaling engineering teams for customers including Qualcomm, and later served as Account Director at UST Global, managing key VLSI and Embedded semiconductor accounts across India and APAC.

Most recently, as Program Director at Tech Mahindra Cerium, he led the integration of Cerium into Tech Mahindra, coordinating customer contracts, delivery operations, and change management through the transition.

Across his career, Vasudevan has built scalable training and mentoring models that convert junior engineers into deployment-ready semiconductor talent — a focus that continues to shape his work at Sophrosyne Semiconductor today.

Sri Harsha Reddy Kaliki is a seasoned engineering professional with 14 years of experience in flow methodology development across Analog, Digital, and Mixed-Signal domains. With deep expertise in building and optimizing design and verification flows, he has consistently driven efficiency, quality, and innovation in semiconductor development processes.

He currently leads the Methodology team at SSIR, where he is responsible for defining and advancing flow strategies that enable cutting-edge chip design. In addition to his core methodology leadership, he is actively driving AI enablement initiatives, exploring how artificial intelligence can transform traditional design flows and accelerate time-to-market.

Saurav Choudhary is a Lead Application Engineer at Real Intent Inc., specializing in static verification and signoff for high-performance CPU, GPU, and NoC designs. His expertise spans Lint, CDC, RDC, connectivity, security, and power verification, with a focus on addressing complex design challenges in collaboration with cross-functional teams.

Prior to joining Real Intent, he was a Digital Design Engineer at NXP Semiconductors, where he worked on RTL and microarchitecture for hardware accelerator IPs. He has co-authored technical papers presented at DAC 2024 and DAC 2025 on advanced static verification methodologies.

Sanathraj Narayan is an AI Manager at LAM Research.